Reversible logic circuits have found emerging attentions in nanotechnology, optical computing, quantum computing and low power design. A programmable logic array (PLA) is a universal circuit which is used to implement combinational logic circuits. The main part of a PLA is its AND array. In this study we propose two types of optimized Reversible programmable logic array (RPLA) circuits. The first type is based on a “2-to-4” AND array, and is proposed for the first time. The second type is based on a “3-to-8” AND array. For each type, we bring some different designs. These circuits are compared with the existing counterparts in terms of number of constant inputs and garbage outputs, delay and the quantum cost and are shown that all parameters in proposed circuits are improved.

Power consumption is one of the most challenging issues in design of electronic circuits. Reversible logic is a solution for power optimization. In this paper, we propose three fault-tolerant serial multiplier designs based on the Reversible logic with error detection capability. The first proposed serial multiplier which is based on the Booth’s algorithm utilizes a new arrangement of Reversible gates. The second proposed serial multiplier for signed numbers is based on a newer algorithm called the K algorithm. This algorithm requires less cost compared to the Booth's algorithm.The third proposed fault-tolerant serial multiplier which is optimized for unsigned number multiplication is based on the conventional Add & Shift method. The comparative results show that the proposed multipliers are much better than the existing designs considering the main criterions used in Reversible logic circuits which include quantum cost, number of gates, number of garbage outputs, delay, and computational complexity.

In recent years, Reversible circuits have drawn high attention due to their usability in power consumption optimization of low power CMOS circuits in addition to quantum computing. On the other hand, fault and error tolerance has been one of the vital characteristics of new circuits because of the increasing susceptibility of these circuits against environmental effects. As adder circuits are the main parts of processing and arithmetic circuits, in this paper, we first propose a new gate to design a parity-preserving full adder, and then, introduce two new fault-tolerant Reversible BCD adders. Based on performed comparisons between the proposed structures and the existing gates and adders, the new full adder and BCD adders are the best or favorable designs according to the number of required gates, hardware complexity, delay and quantum cost.

Reversible logic is one of the new paradigms for power optimization that can be used instead of the current circuits. Moreover, the fault-tolerance capability in the form of error detection or error correction is a vital aspect for current processing systems. In this paper, as the mult iplication is an important operat ion in computing systems, some novel Reversible multiplier designs are proposed with the paritypreserving property which will be useful for error detection. At first, two optimal signed serial multipliers are presented based on the Booth’ s algorithm and its enhanced version called the K-algorithm, ut ilizing the new arrangements of Reversible gates. Then, another low-cost serial multiplier is proposed based on the conventional Add & Shift method to be ut ilized in the applications in which unsigned numbers are used. Finally, a new signed parallel multiplier is proposed based on the Baugh-Wooley method that is useful for speed-critical applications. The comparative results showed that the proposed mult ipliers are much bet ter than the existing designs regarding the main criterions used in Reversible logic circuits including quantum cost, gate count, constant inputs, and garbage outputs.

Reversible logic has been emerged as a promising computing paradigm to design low power circuits in recent years. The synthesis of Reversible circuits is very different from that of non-Reversible circuits. Many researchers are studying methods for synthesizing Reversible combinational logic. Some automated Reversible logic synthesis methods use optimization algorithms Optimization algorithms are used in some automated Reversible logic synthesis techniques. In these methods, the process of finding a circuit for a given function is a very time-consuming task, so it’, s better to design a processor which speeds up the process of synthesis. Application specific instruction set processors (ASIP) can benefit the advantages of both custom ASIC chips and general DSP chips. In this paper, a new architecture for automatic Reversible logic synthesis based on an Application Specific Instruction set Processors is presented. The essential purpose of the design was to provide the programmability with the specific necessary instructions for automated synthesis Reversible. Our proposed processor that we referred to as ARASP is a 16-bit processor with a total of 47 instructions, which some specific instruction has been set for automated synthesis Reversible circuits. ARASP is specialized for automated synthesis of Reversible circuits using Genetic optimization algorithms. All major components of the design are comprehensively discussed within the processor core. The set of instructions is provided in the Register Transform Language completely. Afterward, the VHDL code is used to test the proposed architecture.